P4C174 Datasheet PDF - Semiconductor Corporation

DESCRIPTION
The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset function provides the capability to reset all memory locations to a LOW level.

FEATURES
■ High Speed Address-To-Match - 8 ns Maximum Access Time
■ High-Speed Read-Access Time
    – 8/10/12/15/20/25 ns (Commercial)
    – 15/20/25 ns (Military)
■ Open Drain MATCH Output
■ Reset Function
■ 8-Bit Tag Comparison Logic
■ Automatic Powerdown During Long Cycles
■ Data Retention at 2V for Battery Backup Operation
■ Advanced CMOS Technology
■ Low Power Operation
■ Package Styles Available
    — 28 Pin 300 mil DIP
    — 28 Pin 300 mil Plastic SOJ
■ Single Power Supply
    — 5V±10%