P4C198-20LMB Datasheet PDF - Performance Semiconductor

DESCRIPTION
The P4C198/L and P4C198A/L are 65,536-bit ultra high speed static RAMs organized as 16K x 4. Each device features an active low Output Enable control to eliminate data bus contention. The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables, both active low) for easy system expansion. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply.

FEATURES
■ Full CMOS, 6T Cell
■ High Speed (Equal Access and Cycle Times)
   – 10/12/15/20/25 ns (Commercial)
   – 12/15/20/25/35 ns (Industrial)
   – 15/20/25/35/45 ns (Military)
■ Low Power Operation (Commercial/Military)
■ 5V ± 10% Power Supply
■ Data Retention, 10 µA Typical Current from 2.0V P4C198L/198AL (Military)
■ Output Enable & Chip Enable Control Functions
   – Single Chip Enable P4C198
   – Dual Chip Enable P4C198A
■ Common Inputs and Outputs
■ Fully TTL Compatible Inputs and Outputs
■ Standard Pinout (JEDEC Approved)
   – 24-Pin 300 mil DIP
   – 24-Pin 300 mil SOJ
   – 28-Pin 350 x 550 mil LCC