PCK2011DL Datasheet PDF - Philips Electronics

Overview
The Direct Rambus Clock Generator (DRCG) provides the Channel clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock. Contained in a 24-pin SSOP package, the DRCG provides an off-the-shelf solution for a broad range of Direct Rambus memory applications.

FEATUREs
• High Speed Clock Support Provides a 400MHz differential clock source for Direct Rambus memory systems for an 800MHz data transfer rate.
• Synchronization Flexibility The DRCG includes signals to synchronize the clock domains of the Rambus
Channel with an external system or processor clock.
• Power Management Support The DRCG is able to turn off the Rambus Channel clock to minimize power for mobile and other power-sensitive applications:
    - In the “clock off” mode, the DRCG remains on while the output is disabled, allowing fast transitions between the clock-off and clock-on states. This mode could be used in conjunction with the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC).
    - In the “power down” mode, the DRCG is completely powered down for minimum power dissipation. This mode is used in conjunction with the power down modes of the RDRAMs and RAC.
• Supports Independent Channel Clocking The DRCG supports systems that do not require synchronization of the Rambus clock to another system clock.
• Works with Philips PCK2010 to support Intel CK98 Clock Synthesizer/Driver specification.