PCS2P5T907A Datasheet PDF - PulseCore Semiconductor
Part Name
PCS2P5T907A
Other PDF
no available.
PDF
page
21 Pages
File Size
740.7 kB
MFG CO.
PulseCore Semiconductor
Functional Description
The PCS2P5T907A 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The PCS2P5T907A can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels.
Features
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5nS. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot Insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
LVEPECL input interface
• Selectable differential or single-ended inputs and
ten single ended outputs
• 2.5V Supply Voltage
• Available in TSSOP Package
Applications:
PCS2P5T907A is targeted towards Clock and signal
distribution applications.
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