PDSP16112/A Datasheet PDF - Zarlink Semiconductor Inc

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement.

FEATURES
■ Complex Number (16 + 16) X (16 + 16) Multiplication
■ Full 32 bit Result
■ 20MHz Clock Rate
■ Block Floating Point FFT Butterfly Support
■ -1 times -1 Trap
■ Twos Complement Fractional Arithmetic
■ TTL Compatible I/O
■ Complex Conjugation
■ 2 Cycle Fall Through
■ 144 pin PGA or QFP packages

APPLICATION
■ Fast Fourier Transforms
■ Digital Filtering
■ Radar and Sonar Processing
■ Instrumentation
■ Image Processing