PDSP16256C0 Datasheet PDF - ETC

[ZARLINK]

Description
The PDSP16256 contains sixteen multiplier - accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two’s complement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits.

FEATUREs
● Sixteen MACs in a Single Device
● Basic Mode is 16-Tap Filter at up to 25MHz Sample Rates
● Programmable to give up to 128 Taps with Sampling Rates Proportionally Reducing to 3·125MHz
● 16-bit Data and 32-bit Accumulators
● Can be configured as One Long Filter or Two Half-Length Filters
● Decimate-by-two Option will Double the Filter Length
● Coefficients supplied from Host System or local EPROM

APPLICATIONs
● High Performance Digital Filters