PF48F4000P0ZB Datasheet PDF - Micron Technology

General Description
   The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology.

FEATUREs
• High performance
   – 100ns initial access for Easy BGA
   – 110ns initial access for TSOP
   – 25ns 16-word asychronous page read mode
   – 52 MHz (Easy BGA) with zero WAIT states and
      17ns clock-to-data output synchronous burst
      read mode
   – 4-, 8-, 16-, and continuous word options for burst
      mode
   – Buffered enhanced factory programming (BEFP)
      at 2 MB/s (TYP) using a 512-word buffer
   – 1.8V buffered programming at 1.14 MB/s (TYP)
      using a 512-word buffer
• Architecture
   – MLC: highest density at lowest cost
   – Asymmetrically blocked architecture
   – Four 32KB parameter blocks: top or bottom configuration
   – 128KB main blocks
   – Blank check to verify an erased block
• Voltage and power
   – VCC (core) voltage: 1.7V to 2.0V
   – VCCQ (I/O) voltage: 1.7V to 3.6V
   – Standy current: 65µA (TYP) for 256Mb
   – 52 MHz continuous synchronous read current:
      21mA (TYP), 24mA (MAX)
• Security
   – One-time programmable register: 64 OTP bits,
      programmed with unique information from 
      Micron; 2112 OTP bits available for customer 
      programming
   – Absolute write protection: VPP = VSS
   – Power-transition erase/program lockout
   – Individual zero-latency block locking
   – Individual block lock-down
   – Password access
• Software
   – 25μs (TYP) program suspend
   – 25μs (TYP) erase suspend
   – Flash Data Integrator optimized
   – Basic command set and extended function 
      Interface (EFI) command set compatible
   – Common flash interface
• Density and Packaging
   – 56-lead TSOP package (256Mb only)
   – 64-ball Easy BGA package (256Mb, 512Mb)
   – QUAD+ and SCSP packages (256Mb, 512Mb)
   – 16-bit wide data bus
• Quality and reliabilty
   – JESD47 compliant
   – Operating temperature: –40°C to +85°C
   – Minimum 100,000 ERASE cycles per block
   – 65nm process technology