PI74AVC16835 Datasheet PDF - Pericom Semiconductor Corporation

Product Description
Data flow from A to Y is controlled by Output Enable (OE). The device operates in the transparent mode when LE is HIGH. The A data is latched if CLK is held at a high or low logic level. If LE is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16835 bus driver is designed to drive an array of 133 MHz synchronous memory chips, with minimal undershoot/overshoot noise, and to meet the input signal rise/fall time requirement of memory chips.
The output drivers of this part have an embedded series-resistor. For DIMM module design, no external series termination resistors near the buffer drivers or any other termination resistors are required. This feature simplifies DIMM module layout design, and results in cost savings.

Product Features
• Very high-speed, low-noise universal bus driver with embedded resistor outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and heavy-load applications
• Fast Propagation Delay: 2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packaging (Pb-free and Green available):
    – 56-pin, 240 mil wide plastic TSSOP (A)