PLL103-02XC-R Datasheet PDF - PhaseLink Corporation

DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups).

FEATURES
• Generates 24 output buffers from one input.
• Supports up to four DDR DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Enhanced DDR Output Drive selected by I2C.
• Available in 48 pin SSOP.