PLL103-11 Datasheet PDF - PhaseLink Corporation

FEATURES
• Generates 13 copies of High-speed clock inputs.
• Supports up to three SDRAM DIMMS synchronous clocks.
• Supports 2-wire I2C serial bus interface with readback.
• 50% duty cycle with low jitter.
• Less than 5ns delay.
• Skew between any outputs is less than 250 ps.
• Tri-state pin for testing.
• Frequency up to 150 MHz.
• 3.0V-3.7V Supply range.
• Available in 28-pin 300mil SOIC package.