DESCRIPTIONS
The PLL601-03 is a low cost, high performance and low phase noise clock synthesizer. It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques to allow the user to select the desired multiplier value. The chip accepts crystal or clock inputs ranging from 10 to 30MHz, depening on selected multiplier, and produces outputs clocks up to 198MHz at 3.3V.
FEATURES
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels.
• Reference 10-30MHz crystal or clock.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 198MHz at 3.3V.
• Low phase noise (-126dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 16-Pin SOIC or TSSOP.