QL3012-0PL84C(2002) Datasheet PDF - QuickLogic Corporation

Architecture Overview
The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogics patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

Device Highlights
High Performance & High Density
• 12,000 Usable PLD Gates with 118 I/Os
• 300 MHz 16-bit Counters, 400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes

Easy to Use / Fast Development Cycles
• 100% routable with 100% utilization and complete pin-out stability
• Variable-grain logic cells provide high performance and 100% utilization
• Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled Registered Input Path and Output Enables

Total of 118 I/O Pins
• 110 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades
• Four High Drive input-only pins
• Four High Drive input-only/distributed network pins

Four Low-Skew Distributed Networks
• Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin
• Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control — each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback

High Performance
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz