QL8025-6PV100M Datasheet PDF - QuickLogic Corporation

Device Highlights
Flexible Programmable Logic
• 0.18 µm, six layer metal CMOS process
• 1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O
• Up to 4,002 dedicated flip-flops
• Up to 55.3 K embedded SRAM bits
• Up to 310 I/O
• Up to 335 user available pins
• Up to 320 K system gates
• IEEE 1149.1 boundary scan testing compliant
• Low power capability

Embedded Dual Port SRAM
• Up to twenty-four 2,304 bit dual port high performance SRAM blocks
• RAM/ROM/FIFO wizard for automatic configuration
• Configurable and cascadable aspect ratio

Programmable I/O
• High performance I/O cell with Tco of 3 ns
• Programmable slew rate control
• Programmable I/O standards:
   ► LVTTL, LVCMOS, LVCMOS18, PCI, GTL+, SSTL2, and SSTL3
   ► Independent I/O banks capable of supporting multiple standards in one device
   ► I/O register configurations: Input, Output, Output Enable (OE)

Advanced Clock Network
• Multiple dedicated low skew clock networks
• High drive input-only networks
• Quadrant-based segmentable clock networks
• User programmable Phase Locked Loops (PLL)

Embedded Computational Units (ECUs)
   Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate functions.

Security Features
   The QuickLogic products come with secure ViaLink® technology that protects intellectual property from design theft and reverse engineering. No external configuration memory needed; instant-on at power-up.