S6J3120 Datasheet PDF - Cypress Semiconductor

32-Bit Traveo™ Family Microcontroller Datasheet

   This section provides an overview of the S6J3120 series. The S6J3120 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM® Cortex-R5 CPU as a CPU.  

FEATUREs
This section explains the features of the S6J3120 series.
Cortex-R5 Core
◾ This section explains the Cortex-R5 CPU core.
□ ARM® Cortex®-R5
□ 32-bit ARM architecture
   • 2-instruction issuance super scalar
   • 8-stage pipeline
□ ARMv7/Thumb®-2 instruction set
□ MPU (memory protection) equipped
   • 16-area support
□ ECC support for the TCM ports for RAM
   1-bit error correction and 2-bit error detection
   (SEC-DED)
□ TCM ports
   2 TCM ports
   • ATCM port
   • BTCM port (B0TCM, B1TCM)
□ Caches
   • Instruction cache 16 KB
   • Data cache 16 KB
□ VIC port
   Low latency interrupt
□ AXI master interface
   64-bit AXI interface (instruction/data access)
   32-bit AXI interface (I/O access)
□ AXI slave interface
   64-bit AXI interface (TCM port access)
□ ETM-R5 trace
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