S9S08RN32 Datasheet PDF - NXP Semiconductors.

Features
• 8-Bit S08 central processor unit (CPU)
   – Up to 20 MHz bus at 2.7 V to 5.5 V across
      temperature range of -40 °C to 125 °C
   – Supporting up to 40 interrupt/reset sources
   – Supporting up to four-level nested interrupt
   – On-chip memory
   – Up to 60 KB flash read/program/erase over full
      operating voltage and temperature
   – Up to 256 byte EEPROM with ECC; 2-byte erase
      sector; EEPROM program and erase while executing
      code from flash
   – Up to 4096 byte random-access memory (RAM)
   – Flash and RAM access protection
• Power-saving modes
   – One low-power stop mode; reduced power wait
      mode
   – Peripheral clock enable register can disable clocks to
      unused modules, reducing currents; allows clocks to
      remain enabled to specific peripherals in stop3 mode
• Clocks
   – Oscillator (XOSC) - loop-controlled Pierce
      oscillator; crystal or ceramic resonator
   – Internal clock source (ICS) - containing a frequency-locked-loop (FLL)
      controlled by internal or external
      reference; precision trimming of internal reference
      allowing 1% deviation across temperature range of 0
      °C to 70 °C and -40 °C to 85 °C, 1.5% deviation
      across temperature range of -40 °C to 105 °C, and
      2% deviation across temperature range of -40 °C to
      125 °C; up to 20 MHz
• System protection
   – Watchdog with independent clock source
   – Low-voltage detection with reset or interrupt;
      selectable trip points
   – Illegal opcode detection with reset
   – Illegal address detection with reset
• Development support
   – Single-wire background debug interface
   – Breakpoint capability to allow three breakpoints
      setting during in-circuit debugging
   – On-chip in-circuit emulator (ICE) debug module
      containing two comparators and nine trigger modes
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