ST5481 Datasheet PDF - STMicroelectronics

DESCRIPTION
ST5481 combines ISDN link access and an USB interface to allow a very simple USB/ISDN modem design with all ISDN protocols and upper applications processed into the HOST PC.

HARDWARE FEATURES
S/T ISDN Interface
■ SUPPORTS OSI LEVEL 1 IN CONFORMANCE WITH UIT-T I.430 FOR BASIC ACCESS AT S AND T INTERFACES (ETSI 300012/ANSI T1.605)
■ LINE INTERFACE TRANSFORMER DIRECT DRIVE
■ FULL-DUPLEX TRANSMISSION AT 192KBps ON SEPARATE TRANSMIT AND RECEIVE TWISTED PAIRS USING ALTERNATE MARK INVERSION (AMI) LINE CODING
■ 2 B CHANNELS AT 64KBps EACH PLUS 1 D CHANNEL AT 16KBps
■ ALL I.430 WIRING CONFIGURATIONS SUPPORTED INCLUDING PASSIVE BUS FOR TE’S DISTRIBUTED POINT TO POINT AND POINT TO MULTIPOINT
■ MULTIFRAME SUPPORT
■ ANALOG PART: INCLUDED WITH ADAPTIVE DETECTION THRESHOLD AND EQUALIZER

USB Interface
■ USB 1.0 SPECIFICATION FULL COMPLIANCE, 1.1 SPECIFICATION COMPATIBILITY (1.1 POWER MANAGEMENT COMPLIANCE), 12 MBps FULL SPEED
■ ON-CHIP USB TRANSCEIVER WITH DIGITAL PLL
■ 6 ISOCHRONOUS ENDPOINTS FOR B1, B2, D CHANNELS DATA.INTERRUPT ENDPOINT FOR I430
■ ISDN PROTOCOL AND DATA.CONTROL ENDPOINT FOR USB STANDARD PLUS VENDOR SPECIFIC REQUEST
■ COMMUNICATION DEVICE CLASS AND VENDOR REQUESTS
■ BUS OR SELF POWERED APPLICATION (PIN PROGRAMMABLE)
■ ONNOW POWER MANAGEMENT (D0,D2,D3) SUSPEND MODE COMPLIANCE
■ PIN PROGRAMMABLE HIGH/LOW POWER USB DEVICE REGISTRATION, WAKE-UP CAPABILITY, USB DEVICE IDENTIFICATION

GENERAL
– USB hot plug and play interface.
– Control access and interrupt handling provided through the USB interface.
– All FIFOS and FIFOS management needed included for USB/ISDN data processing.
– Internal PLL to generate the USB 48MHz clock from a 15.36MHz crystal.
– Internal regulator for 3.3V generation from USB bus 5V.
– 48 pin TQFP package.
– 0.35 micron HCMOS 6 process.