STLVDS3486(2006) Datasheet PDF - STMicroelectronics

Description
The STLVDS3486, is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a valid logical output state with a 3.3V supply rail. It also provides a valid logical output state with a ±100mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1V of ground potential difference between two LVDS nodes.

FEATURE summary
■ meets or exceeds the requirements of ansi TIA/EIA-644 standard
■ Operates with a single 3.3V supply
■ Designed for signaling rate up to 400Mbps
■ Differential input thresholds ±100mV max
■ Typical propagation delay time of 2.5ns
■ Power dissipation 60mW typical per receiver at 200MHz
■ Low voltage TTL (LVTTL) logic output levels
■ Pin compatible with the MC3486 and SN65LVD3486
■ Open circuit fail safe
■ ESD protection:
    7KV receiver pins
    3KV all pins vs gnd