24FC65T View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'24FC65T' PDF : 14 Pages View PDF
24FC65
FIGURE 7-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 Write command initiated at byte 0 of page 3 in the array;
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache cache • • • cache cache page 1 cache page 2
byte 0 byte 1
byte 7 bytes 8-15 bytes 16-23
•••
cache page 7
bytes 56-63
3 Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
4 Remaining pages in cache are written
to sequential pages in array.
page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2
page 3
page 4 • • • page 7 array row n + 1
5 Last page in cache written to page 2 in next row.
FIGURE 7-2: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
1 Write command initiated; 64 bytes of data
2 Last 2 bytes ‘roll ever’
3
loaded into cache starting at byte 2 of page 0.
to beginning.
cache cache cache • • • cache cache page 1 cache page 2
byte 0 byte 1 byte 2
byte 7 bytes 8-15 bytes 16-23
•••
cache page 7
bytes 56-63
Last 2 bytes
loaded into page
0 of cache.
4
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
5 Remaining bytes in cache
are written sequentially to
array.
array row n
page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4
page 0 page 1 page 2
page 3
6 Last 3 pages in cache written to next row in array.
•••
byte 7 page 4
page 4
• • • page 7
• • • page 7
array row n+1
DS21125E-page 10
2004 Microchip Technology Inc.
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