24FC65T View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'24FC65T' PDF : 14 Pages View PDF
24FC65
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
1 MHz Bus
Min Max
Units
Remarks
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START hold time
FCLK
THIGH
TLOW
TR
TF
THD:STA
0
1000 kHz
500
—
ns
500
—
ns
—
300
ns (Note 1)
—
100
ns (Note 1)
250
—
ns After this period the first clock pulse is
generated
START setup time
TSU:STA
250
—
ns Only relevant for repeated START
Data input hold time
THD:DAT
0
—
ns
Data input setup time
TSU:DAT
100
—
ns
STOP setup time
TSU:STO
250
—
ns
Output valid from clock
TAA
—
350
ns (Note 2)
Bus free time
TBUF
500
—
ns Time the bus must be free before a
new transmission can start
Write cycle time
TWR
—
5 ms/page (Note 3)
Endurance
High Endurance Block
Rest of Array
10M
1M
— cycles 25°C, Vcc = 5.0V, Block Mode
—
(Note 4)
Note 1: Not 100 percent tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOPs.
3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:STA
THD:DAT
TSU:DAT TSU:STO
SDA
IN
TSP
TAA
TAA
TBUF
SDA
OUT
2004 Microchip Technology Inc.
DS21125E-page 3
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