68901N04 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'68901N04' PDF : 33 Pages View PDF
MK68901
Figure 17 : USART Control Register (UCR).
÷ 16/÷ 1 : When this bit is zero, data will be clocked
into and out of the receiver and transmit-
ter at the frequency of their respective
clocks. When this bit is loaded with a one,
data will be clocked into and out of the re-
ceiver and transmitter at one sixteenth
the frequency of their respective clocks.
Additionally, when placed in the divide by
sixteen mode, the receiver data transition
resynchronization logic will be enabled.
WL0-WL1 :Word Length Control. These two bits set
the length of the data word (exclusive of
start bits, stop bits, and parity bits as fol-
lows:
WL1 WL0
00
01
10
11
Word Length
8 Bits
7 Bits
6 Bits
5 Bits
ST0-ST1 : Start/stop bit control (format control).
These two bits set the format as follows
ST1 ST0 Start Bits StopBits
Format
00
0
01
1
†1 0
1
11
1
0
SYNC
1
ASYNC
11/2
ASYNC
2
ASYNC
:
PARITY : Parity Enabled. When set (”1”), parity will
be checked by the receiver, parity will be
calculated, and a parity bit will be inserted
by the transmitter. When cleared (”0”) no
parity check will be made and no parity bit
will be inserted for transmission.
V000363
For a word length of 8 the MFP calculates
the parity and appends it when transmit-
ting a sync character. For shorter
lengths, the parity must be stored in the
Sync Character Register (SCR) along
with the sync character.
E/O :
Even-Odd. When set (”1”), even parity
will be used if parity is enabled. When
cleared (”0”), odd parity will be used if pa-
rity is enabled.
Note that the synchronous or asynchronous format
may be selected independently of a ÷ 1 or ÷ 16 clock.
Thus it is possible to clock data synchronously into
the device but still use start and stop bits. In this
mode, all normal asynchronous format features still
apply. Data will be shifted in after a start bit is en-
countered, and a stop bit will be checked to deter-
mine proper framing. If a transmit underrun condi-
tion occurs, the output will be placed in a marking
state, etc. It is conversely possible to clock data in
asynchronously using a synchronous format. There
is data transition detection logic built into the receive
clock circuitry which will re-synchronize the internal
shift clock on each data transition so that, with suf-
ficienty frequent data transitions, start bits are not re-
quired. In this mode, all other common synchronous
features function normally. This re-synchronization
logic is only active in ÷ 16 clock mode.
RECEIVER
The receiver section of the USART is configured by
the UCR as previously described. The status of the
receiver can be determined by reading and writing
to the Receiver Status Register (RSR). The RSR is
configured as follows :
14/33
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