68901N04 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'68901N04' PDF : 33 Pages View PDF
MK68901
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA = 0°C to 70°C)
Number
Characteristic
V al u e
MK68901-4 MK68901-5 Unit
Fig. Note
1
CS, DS Width High
Min. Max. Min. Max.
50
35
ns 21,22 5
2
R/W, A1-A5 Valid to Falling CS (setup)
3
Data Valid Prior to Falling CLK
4
CS, IACK Valid to Falling Clock (setup)
0
0
280
0
50
45
ns 21,22
ns
22
ns 21-24 3
5
CLK Low to DTACK Low
6
CS, DS or IACK High to DTACK High
220
180 ns 21,22
60
55 ns 21-24
7
CS, DS or IACK High to DTACK Tri-state
8
DTACK Low to Data Invalid (hold time)
9
CS, DS or IACK High to Data Tri-state
100
0
0
50
95 ns 21-24
ns
22
50 ns 21,23,24
10 CS or DS High to R/W, A1-A5 Invalid (hold time) 0
0
ns 21,22
11 Data Valid from CS Low
310
260 ns
21
3,6
12 Read Data Valid to DTACK Low (setup)
50
50
ns
21
13 DTACK Low to DS, CS or IACK High (hold time) 0
0
ns 21-23
14 IEI Low to Falling CLK (setup)
50
50
ns 23,24
15 IEO Valid from Clock Low (delay)
16 Data Valid from Clock Low (delay)
17 IEO Invalid from IACK High (delay)
18 DTACK Low from Clock High (delay)
180
180 ns
23
1
300
300 ns
23
150
150 ns 23, 24
180
165 ns 23, 24
19 IEO Valid from IEI Low (delay)
100
100 ns
24
1
20 Data Valid from IEI Low (delay)
21 Clock Cycle Time
220
220 ns
24
250 1000 200 1000 ns
21
22 Clock Width Low
23 Clock Width High
110
90
110
90
ns
21
ns
21
24 CS, IACK Inactive to Rising Clock (setup)
25 I/O Minimum Active Pulse Width
26 IACK Width High
27 I/O Data Valid from Rising CS or DS
28 Receiver Ready Delay from Rising RC
100
80
ns 21-23 4,5
100
100
ns
25
2
2
T CL K 23-24
2
450
450 ns
26
600
600 ns
27
29 Transmitter Ready Delay from Rising TC
30 Timer Output Low from Rising Edge of CS or DS
(A & B) (reset T OUT)
31
TOUT Valid from Internal Timeout
600
450
2 tCLK
+ 300
600 ns
28
450 ns
29
7
2 tCL K ns
29
2
+ 300
32 Timer Clock Low Time
110
90
ns
29
21/33
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