68901N04 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'68901N04' PDF : 33 Pages View PDF
MK68901
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA = 0°C to 70°C)
Number
Characteristic
V al u e
MK68901-4 MK68901-5 Unit
Fig. Note
Min. Max. Min. Max.
33 Timer Clock High Time
110
90
ns
29
34 Timer Clock Cycle Time
250 1000 200 1000 ns
29
35 RESET Low Time
2
1.8
µs
30
36 Delay to Falling INTR from External Interrupt
Active Transition
380
380 ns
25
37 Transmitter Internal Interrupt Delay from Falling
Edge of TC
550
550 ns
28
38 Receiver Buffer Full Interrupt Transition Delay
from Rising Edge of RC
800
800 ns
27
39 Receiver Error Interrupt Transition Delay from
Falling Edge of RC
800
800 ns
27
40 Serial in Set Up Time to Rising Edge of RC
80
70
ns
27
(divide by one only)
41 Data Hold Time from Rising Edge of RC
(divide by one only)
350
325
ns
27
42 Serial Output Data Valid from Falling Edge of TC
(÷1)
440
420 ns
28
43 Transmitter Clock Low Time
500
450
ns
28
44 Transmitter Clock High Time
45 Transmitter Clock Cycle Time
46 Receiver Clock Low Time
500
450
ns
28
1.05 ∞ 0.95 ∞ µs
28
500
450
ns
27
47 Receiver Clock High Time
500
450
ns
27
48 Receiver Clock Cycle Time
1.05 ∞ 0.95 ∞ µs
27
49 CS, IACK, DS Width Low
80
80 T CL K 29
2
50 Serial Output Data Valid from Falling Edge of TC
(÷16)
490
370 ns
28
Notes :
1. IEO only goes low if no acknowledgeable interrupt is
pending. If IEO goes low, DTACK and the data bus re-
main tri-stated.
2. TCLK refers to the clock applied to the MFP CLK input
pin. tCLK refers to the timer clock signal, regardless of
whether that signal comes from the XTAL 1/XTAL2crys-
tal clock inputs or the TAI or TBI timer inputs.
3. If the setup time is not met, CS or IACK will not be reco-
gnized until the next falling CLK.
4. If this setup time is met (for consecutive cycles), the mi-
nimum hold-off time of one clock cycle will be obtained.
If not met, the hold-off will be two clock cycles.
5. CS is latched internally, therefore if spec’s 1 and 24 are
met then CS may be reasserted before the rising clock
and still terminate the current bus cycle.The new bus cy-
cle will be delayed by the MK68901 until all appropriate
internal operations have completed.
6. Although CS and DTACK are synchronized with the
clock, the data out during a read cycle is asynchronous
to the clock, relying only on CS for timing.
7. Spec. 30 applies to timer outputs TAO and TBO only.
22/33
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