73K324L View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'73K324L' PDF : 30 Pages View PDF
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
CONTROL REGISTER 2
D7
CR2
0
100
D6
SPEC
REG
ACCESS
D5
CALL
INIT
D4
TRANSMIT
S1
D3
16 WAY
D2
RESET
DSP
D1
TRAIN
INHIBIT
D0
EQUALIZER
ENABLE
BIT NO.
D0
D1
D2
D3
D4
D5
D6
D7
NAME
Equalizer
Enable
Train Inhibit
RESET DSP
16 Way
Transmit
S1
Call Init
Special
Register
Access
N/A
CONDITION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DESCRIPTION
The adaptive equalizer is in its initialized state.
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
The adaptive equalizer is active.
The adaptive equalizer coefficients are frozen.
The DSP is inactive and all variables are initialized.
The DSP is running based on the mode set by other
control bits
The receiver and transmitter are using the same decision
plane (based on the Modulator Control Mode).
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
The transmitter when placed in alternating Mark/Space
mode transmits 0101 . . . . scrambled or not dependent
on the bypass scrambler bit and Modulation mode.
When this bit is 1 and only when the transmitter is placed
in alternating Mark/Space mode by CR1 bits D7, D6, an
unscrambled repetitive double dibit pattern of 00 and 11
at 1200 bit/s (S1) is sent.
The DSP is setup to do demodulation and pattern
detection based on the Various mode bits. Both answer
tones are detected in Demod Mode concurrently; TR D0
is ignored.
The DSP decodes call progress, calling tones,
unscrambled mark, and 2100 Hz and 2225 Hz answer
tones.
Normal CR3 access.
Setting this bit and addressing CR3 allows access to the
SPECIAL REGISTER. See the SPECIAL REGISTER for
details.
Must be 0 for normal operation.
Page: 14 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
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