73K324L View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'73K324L' PDF : 30 Pages View PDF
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
SPECIAL REGISTER (continued)
BIT NO.
D3
D2, D1
NAME
TXD
SOURCE
SIGNAL
QUALITY
LEVEL
SELECT
DESCRIPTION
This bit selects the transmit data source; either the TXD pin if ZERO or the
TXDALT if this bit is a ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1
override either of these sources.
The signal quality indicator is a logical zero when the signal received is
acceptable for low error rate reception. It is determined by the value of the
Mean Squared Error (MSE) calculated in the decision process when compared
to a given threshold. This threshold can be set to four levels of error rate. The
SQI bit will be low for good or average connections. As the error rate crosses
the threshold setting, the SQI bit will toggle at a 1.66 ms rate. Toggling will
continue until the error rate indicates that the data pump has lost convergence
and a retrain is required. At that point the SQI bit will be a ONE constantly. The
SQI bit and threshold selection are valid for QAM and DPSK only.
D2 D1
00
01
10
11
TYPICAL
THRESHOLD VALUE
10-5
10-6
10-4
10-3
UNITS
BER (default)
BER
BER
BER
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This
register provides functions to the 73K324L user that are not necessary in normal
communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access,
CR2 bit D6 must be returned to a ZERO.
ID REGISTER
ID
D7
D6
D5
D4
D3
D2
D1
D0
110
ID
ID
ID
ID
X
X
X
X
3
2
1
0
BIT NO.
D7, D6,
D5, D4
D3-D0
NAME
Device
Identification
Signature
Undefined
CONDITION DESCRIPTION
D7 D6 D5 D4 Indicates Device:
0 0 X X 73K212AL or 73K322L or 73K321L
0 1 X X 73K221AL or 73K302L
1 0 X X 73K222AL, 73K222BL
1 1 0 0 73K224L
1 1 1 0 73K324L
1 1 0 0 73K224BL
1 1 1 0 73K324BL
Mask in software
Page: 16 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
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