78P2352-IELR/F View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'78P2352-IELR/F' PDF : 42 Pages View PDF
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
CONTROL PINS
NAME
FRST
LPBKx
CKMODE
PIN
78
17, 18
15
TYPE DESCRIPTION
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRSTx will resume FIFO operation.
• Low: Channel 1 FRST assertion
CIT
• Float: Normal operation
• High: Channel 2 FRST assertion
Because the internal VCO clock and off-chip transmit clocks may not be
stable during transmit power-up, it is recommended to always reset the FIFOs
after powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
Analog Loopback Selection:
• Low: Normal operation
CIT
• Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
• High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
• Low: Parallel transmit clock is input to the 78P2352.
• Float: Parallel transmit clock is input to the 78P2352. Loop-timing
mode enabled.
CIT
• High: Parallel transmit clock is output from the 78P2352
In SERIAL mode (SDI_PAR low):
• Low: Reference clock is synchronous to transmit clock and data.
Data is clocked in with SIxCKP/N and passed through a FIFO
• Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
• High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
Page: 19 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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