9S12HA48 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HA48' PDF : 790 Pages View PDF
Chapter 2
Port Integration Module (S12HYPIMV1)
Revision History
Version
Number
01.00
01.05
Revision
Date
Effective
Date
12 April 2008
18 Dec 2008
Author
Description of Changes
Initial version
update typo for PER1AD register description
2.1 Introduction
2.1.1 Overview
The S12HY Family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
• Port A associated with the IRQ, XIRQ interrupt inputs and API_EXTCLK. Also associated with
the LCD driver output
• Port B used as general purpose I/O and LCD driver output
• Port R associated with 2 timer module - port 7-4 inputs can be used as an external interrupt source.
Also associated with the LCD driver output. PR also associated with the IIC
• Port T associated with 2 timer module. Also associated with the LCD driver output. It can be used
as external interrupt source
• Port S associated with 1 SCI module, 1 IIC module and 1 MSCAN, and PWM. Port 7-6 can be used
as an external interrupt source
• Port P connected to the PWM, also associated with LCD driver output
• Port H associated with 1 SPI, 1 IIC. Also associated with LCD driver output
• Port AD associated with one 8-channel ATD module. It an be used as an external interrupt source
• Port U/V associated with the Motor driver output. Also PV3-0 associated with 1 SPI, 1 IIC and 4
PWM channels. PU0/PU2/PU4/PU6 and PV0/PV2/PV4/PV6 associated with TIM0 channels 0 -3
and TIM1 channels 0 -3
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices. Port U/V have register bits to select the slew rate control.
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
53
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