9S12HA64 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'9S12HA64' PDF : 790 Pages View PDF
2.3.24 Port S Data Direction Register (DDRS)
Port Integration Module (S12HYPIMV1)
Address 0x024A
R
W
Reset
7
DDRS7
0
1 Read: Anytime.
Write: Anytime.
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 2-22. Port S Data Direction Register (DDRS)
Access: User read/write1
1
0
DDRS1
DDRS0
0
0
Table 2-21. DDRS Register Field Descriptions
Field
7
DDRS
Description
Port S data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, the IIC determines the pin direction, it will force as open-drain output
Else if PWM3 is routing to PS and PWM3 is enabled it will force as output.
6
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM2 is routing to PS and PWM2 is enabled it will force as output.
5
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM1 is routing to PS and PWM1 is enabled it will force as output.
4
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, it will force as open-drain output
Else if PWM0 is routing to PS and PWM0 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
87
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