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9S12HY32 View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
MFG CO.
9S12HY32
Freescale
Freescale Semiconductor Freescale
'9S12HY32' PDF : 790 Pages View PDF
Port Integration Module (S12HYPIMV1)
Table 2-49. DDRR Register Field Descriptions
Field
7
DDRR
Description
Port R data direction
This register controls the data direction of pin 7.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
6
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction
This register controls the data direction of pin 6.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
5
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction
This register controls the data direction of pin 5.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
4
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction
This register controls the data direction of pin 4.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
3-0
DDRR
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction
This register controls the data direction of pin 3-0.This register configures pin as either input or output.
If TIM1/TIM0 are routing to the PR and TIM1/TIM0 output compare functions are enabled, it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
MC9S12HY/HA-Family Reference Manual, Rev. 1.02
Freescale Semiconductor
109
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