A4982
DMOS Microstepping Driver with Translator
And Overcurrent Protection
OUT2B
OUT2A OUT1A
OUT1B
GND
GND
R4
R5
VBB
C2
C6
C3
U1
BULK
CAPACITANCE
R3
C1
GND
GND
C4
GND
C5 ROSC
VDD
OUT2B
OUT2A
R4
C7
OUT1A
R5
OUT1B
C6
C3
OUT2B
VBB2
ENABLE
GND
CP1
CP2
PAD
A4982
OUT1B
VBB1
DIR
GND
REF
STEP
C4
C1
C5
ROSC
VBB
C2
VDD
Figure 9. ET package typical application and circuit layout
VDD
8V
GND
VREG
10 V
GND
Pin Circuit Diagrams
VBB
GND
40 V
GND
PGND GND
VBB
SENSE
DMOS
Parasitic
GND
VREG
VBB
VCP
CP1
CP2
8V
GND
GND
GND
STEP
MS1
MS2
DIR
ENABLE
RESET 8 V
SLEEP
GND
GND
VBB
DMOS
Parasitic
GND
OUT
DMOS
Parasitic
Allegro MicroSystems, Inc.
13
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com