A4984
DMOS Microstepping Driver with Translator
And Overcurrent Protection
Application Layout
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A4984 must be soldered directly onto the board. On the under-
side of the A4984 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4984, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as close
to the device supply pins as possible. The ceramic capacitor (C7)
should be closer to the pins than the bulk capacitor (C2). This
is necessary because the ceramic capacitor will be responsible
for delivering the high frequency current components.The sense
resistors, RSx , should have a very low impedance path to ground,
because they must carry a large current while supporting very
accurate voltage measurements by the current sense comparators.
Long ground traces will cause additional voltage drops, adversely
affecting the ability of the comparators to accurately measure the
current in the windings. The SENSEx pins have very short traces
to the RSx resistors and very thick, low impedance traces directly
to the star ground underneath the device. If possible, there should
be no other components on the sense circuits.
OUT2B
OUT2A OUT1A
OUT1B
GND
R4
R5
GND
A4984
PCB
Thermal Vias
Solder
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
OUT2B
OUT2A
R4
C7
OUT1A
R5
OUT1B
C7
U1
C1
C3
C4
C6
ROSC
GND
GND
BULK
C2
VDD
VBB
CAPACITANCE
OUT2B
ENABLE
GND
PAD
C3
CP1
CP2
C4
VCP
A4984
C6
ROSC
ES package configuration shown
OUT1B
DIR
GND
REF
STEP
VDD
C1
C2
VDD
VBB
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com