A6273KA View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A6273KA' PDF : 11 Pages View PDF
6273
8-BIT LATCHED
DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
STROBE
OUTPUTx
50%
t su(D) t h(D)
50%
t PLH
10%
tr
50%
t su(D) t h(D)
t PHL
90%
tf
Dwg. WP-036-1
Input Active Time Before Strobe
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Input Active Time After Strobe
(Data Hold Time), th(D) ................................................... 20 ns
Input Pulse Width, tw(D) ...................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
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