A6273KA View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A6273KA' PDF : 11 Pages View PDF
6273
8-BIT LATCHED
DMOS POWER DRIVER
Terminal No.
1
2
Terminal Name
CLEAR
IN1
3
IN2
4
OUT1
5
OUT2
6
OUT3
7
OUT4
8
IN3
9
IN4
10
GROUND
11
STROBE
12
IN5
13
IN6
14
OUT5
15
OUT6
16
OUT7
17
OUT8
18
IN7
19
IN8
20
LOGIC SUPPLY
TERMINAL DESCRIPTIONS
Function
When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN1 = HIGH, OUT1 = LOW).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN2 = HIGH, OUT2 = LOW).
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN3 = HIGH, OUT3 = LOW).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN4 = HIGH, OUT4 = LOW).
Reference terminal for all voltage measurements.
A CMOS dynamic input to all latches. Data on each INx terminal is loaded
into its associated latch on a low-to-high STROBE transition.
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN5 = HIGH, OUT5 = LOW).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN6 = HIGH, OUT6 = LOW).
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
Current-sinking, open-drain DMOS output.
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN7 = HIGH, OUT7 = LOW).
CMOS data input to a latch. When strobed, the output then inverts the data
input (IN8 = HIGH, OUT8 = LOW).
(VDD) The logic supply voltage (typically 5 V).
www.allegromicro.com
Share Link: 
