A81L801UG-70F View Datasheet(PDF) - AMIC Technology
Part Name
Description
MFG CO.
A81L801UG-70F
AMIC Technology
'A81L801UG-70F' PDF : 47 Pages View PDF
A81L801
Word/Byte Configuration
The BYTE_F pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE_F pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE_F and OE .
If the BYTE_F pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE_F and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CE_F and OE pins to VIL. CE_F is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH all the time
during read operation. The BYTE_F pin determines whether
the device outputs array data in words and bytes. The internal
state machine is set for reading array data upon device power-
up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains enabled
for read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE_F to VIL, and
OE to VIH. For program operations, the BYTE_F pin
determines whether the device accepts program data in bytes
or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has details
on programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the auto-select command sequence,
the device enters the auto-select mode. The system can then
read auto-select codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard read
cycle timings apply in this mode. Refer to the "Auto-select
Mode" and "Auto-select Command Sequence" sections for
more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables and
timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 -
I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when the CE_F &
RESET pins are both held at VCC_F ± 0.3V. (Note that this is
a more restricted voltage range than VIH.) If CE_F and RESET
are held at VIH, but not within VCC_F ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) before it is
ready to read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE_F , WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep mode
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tri-states all
data output pins, and ignores all read/write attempts for the
duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When
RESET is held at VSS ± 0.3V, the device draws CMOS
standby current (ICC4). If RESET is held at VIL but not within
VSS ± 0.3V, the standby current will be greater.
PRELIMINARY (March, 2005, Version 0.0)
11
AMIC Technology, Corp.
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