Timing Waveforms (continued)
Read Cycle 3 (1)
Address
OE
CE_S
tRC
tAA
tOE
tOLZ
5
tACE1
A81L801
tOH
DOUT
tACE2
tCLZ25
tOHZ5
tCHZ25
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE_S = VIL.
3. Address valid prior to or coincident with CE_S transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE_S is low.
Write Cycle 1 (6)
(Write Enable Controlled)
Address
CE_S
WE
DIN
DOUT
(4)
tAS1
tWC
tAW
tCW5
tWR3
tWP2
tWHZ
tDW
tDH
tOW
PRELIMINARY (March, 2005, Version 0.0)
41
AMIC Technology, Corp.