Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Address
CE_S
WE
DIN
DOUT
(4)
tAS1
tWC
tAW
tCW5
tCW5
tDW
tWHZ7
tWR3
tDH
A81L801
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE_S , and a low WE .
3. tWR is measured from the earliest of CE_S or WE going high going low to the end of the Write cycle.
4. If the CE_S low transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE_S going low going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (March, 2005, Version 0.0)
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AMIC Technology, Corp.