A8507
LED Backlight Driver for LCD Monitors and Televisions
Application Information
PCB Layout Guidelines As with any switching power supply,
care should be taken in laying out the board. A switching power
supply has sources of high dv/dt and high di/dt which can cause
malfunction. All general norms should be followed for board
layout. Refer to figure 14 for a typical application schematic. The
A8507 evaluation board provides a useful model for designing
application circuit layouts.
The following guidelines should be observed:
• Place the supply bypass capacitor (C5) close to the VIN pin and
the ground plane.
• Route analog ground, digital signal ground, LED ground
(LGND pin), and power ground (PGND pin) separately. Con-
nect all these grounds at the common ground plane under the
A8507, serving as a star ground.
• Place the input capacitors (C1, C2), inductor (L1), boost diode
(D1), MOSFET (Q1), and output capacitors (C3, C4) so that
they form the smallest loop practical. Avoid long traces for
these paths.
• Place the resistors RFSET and RISET, and the compensation com-
ponents (Rz and Cz) close to the FSET, ISET, and COMP pins,
respectively. Connect the other ends to the common star ground.
• A8507 has 50 kΩ internal pull-down resistors on the EN and
PWM pins to keep these pins low while driving through tri-state
state (for example, shutdown). Add external resistors R2 and
R3 between the EN and PWM pins and ground, for added noise
immunity. Connect these resistors close to the pins and return to
the common star ground.
• Sense voltage across RSC with smaller length traces. Place the
SENP and SENN traces as close to each other as possible to
minimize noise pickup. Connect the SENN trace to the negative
end of the resistor and do not connect it to power ground plane.
• Provide a substantial copper plane near MOSFET Q1 and the
IC, to provide good thermal conduction.
• Place ROVP as close as possible to the OVP pin. A long trace
between ROVP and the OVP pin may pick up switching noises
and cause overvoltage protection to trip prematurely.
VBAT
8 to 21 V
C1
P
VBIAS
4.5 to 5.5 V
L1
D1
Q1
C2
RSC
C3
ROVP
10
P
7
6
8
P
DRIVER SENP SENN OVP
11 VIN
VOUT
C4
8 LEDs per string
R1 C5
23 FAULT
A8507
(LP package)
LED1
16
R2
R3
24 EN
2 PWM
COMP
RFSET 15
RISET14 FSET
12 ISET
LED2
17
LED3 18
LED4
20
Rz1
NC
3
LED5
21
Cz1
NC
5
9 NC
GND GND
PAD
LED6
22
LGND PGND
1 13
19
4
P
R2, R3 optional (A8507 has
internal pull-down resistors)
Figure 14. Typical application circuit
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com