AC206-DS02-R View Datasheet(PDF) - Broadcom Corporation
Part Name
Description
MFG CO.
'AC206-DS02-R' PDF : 70 Pages View PDF
Preliminary Data Sheet
07/08/02
AC206
Pin Name
PROM_CS
PROM_CLK (LED_D[6])
PROM_OUT (LED_D[5])
PROM_IN (LED_D[7])
Pin Name
MDC (PROM_CS)
MDIO
Pin Name
M100COL_LOCAL*
M100ACTO*
M100ACTI_0*
(M100ACTO*)
M100ACTI_1*
M100ACTI_2*
M100COL_SYS*
M100CRS_SYS*
MS100D4
MS100D3
MS100D2
MS100D1
MS100D0
MS100D_EN*
MS100D_CLK
Pin #
127
124
123
125
Table 8: EEPROM Interface
Type
O
O
O
I,D
Description
PROM chip select. Connected to Chip Select pin of 93C46 serial
EEPROM
PROM Clock. Connected to CLK pin of 93C46 serial EEPROM
PROM Data Out. Connected to Data_In pin of 93C46 serial
EEPROM
PROM Data In. Connected to Data_Out pin of 93C46 serial
EEPROM
Pin #
127
128
Table 9: MDC/MDIO Interface
Type
I,U
I/O,D
Description
Clock signal between the external device and PHY registers for
communication synchronization
Data Input/Output. It is a bi-directional data interface used by the
external device to access only the internal PHY registers within
AC206. This pin has internal pull-down register.
Table 10: 100 Mbps Internal Repeater Bus
Pin #
3
4
4
6
7
2
8
14
13
12
11
9
1
16
Type
I/O, U
O, U
I,U
I,U
I,U
I/O,U
I/O,U
I/O,D
I/O,D
I/O,D
I/O,D
I/O,D
I/O,U
I/O, U,
S
Description
100M Local Collision. Input when ChipID = 00. Active low to
indicate collision on all other ChipIds.
Output to ChipID=00 for ChipID≠00 to signal local activity. This
signal is pure combinational logic and is not in sync with any clock
source. (Refer to next 3 signals).
Input for ChipID=00 from ChipID≠00 M100ACTO* pins to indicate
activities. Open on all other ChipIDs.
Connected from ChipID=00 to ChipID=10 M100ACTO* to sense
activities. Open on all other ChipIDs.
Connected from ChipID=00 to ChipID=11 M100ACTO* to sense
activities. Open on all other ChipIDs.
ChipID=00 drives this pin the same as 100COLBP* to indicate
local collision.
ChipID=00 drives this pin the same as 100CRSBP* to indicate
local activity.
Multiple/Stacked Data Group. Transmit and receive data in de-
scrambled 5B data groups for multiple devices. Data is sampled
at the rising edge of MS100D_CLK and driven out on falling edge
of MS100D_CLK.
Multiple/Stacked Data Enable. Active-low when data is valid.
Signal is driven out on the falling edge of MS100D_CLK, and
sampled at the rising edge of MS100D_CLK.
Multiple/Stacked Data Clock. The bi-directional non-continuous
25 MHz recovered clock for synchronizing with MS100D[4:0], and
MS100D_EN*.
Document AC206-DS05-405-R
Broadcom
Pin Descriptions Page 15
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