AC206
Preliminary Data Sheet
07/08/02
RECEIVE ERROR COUNT
Table 34: Receive Error Count
Register
Bit
21.[15:0
]
Name
Receive Error
Count
Description
Mode
Count number of receiving packets with error. This register can RO
only be cleared by reset (software or hardware).
Default
0000
POWER MANAGEMENT REGISTER
Register Bit Name
22.[15:14]
22.13
Reserved
PD_PLL
22.12
22.11
PD_EQUAL
PD_BT_RCVR
22.10
22.9
PD_LP
PD_EN_DET
22.8
PD_FX
22.[7:6]
22.5
Reserved
MSK_PLL
22.4
MSK_EQUAL
22.3
MSK_BT_RCVR
22.2
MSK_LP
22.1
MSK_EN_DET
22.0
MSK_FX
Table 35: Power Management Register
Description
1=Power down PLL circuit
1=Power down equalizer circuit
1=Power down 10BASE-T receiver
1=Power down link pulse receiver
1=Power down energy detect circuit
1=Power down FX circuit
0=Force power up PLL circuit
0=Force power up equalizer circuit
0=Force power up 10BASE-T receiver
0=Force power up link pulse receiver
0=Force power up energy detect circuit
0=Force power up FX circuit
Mode
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
Default
00
X
X
X
X
X
X
00
X
X
X
X
X
X
Page 30 PHY Registers
Broadcom
Document AC206-DS05-405-R