Preliminary Data Sheet
07/08/02
TRANSCEIVER MODE REGISTER
Table 36: Transceiver Mode Register
Register
Bit
23.15
23.14
23.13
23.12
23.11
23.10
23.9
23:8
23.7
23:6
23.5
23.[4:0]
Name
Reserved
Reserved
Clk_rclk_save
Reserved
Scramble
disable
Serial bt
enable
Pcsbp
Age timer en
Reserved
Reserved
Force re-adapt
Dlock drop
counter
Description
1 = set rclk save mode. Rclk is hut off after 64 cycles of each
packet
1 = disable scrambler
1 = enable serial bt mode
1 = enable PCS bypass mode
1 = enable age timer in adaptation
0 = disable age timer in adaptation.
1 = force adaptation to re-adapt
Writing a 1 to this bit forces adaptation to re-adapt. This bit is
always read as 0.
D lock drop counter
AC206
Mode
RO
RO
RW
RO
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
RO
0
RO
0
RO
0
RO
XXXXX
Document AC206-DS05-405-R
Broadcom
PHY Registers Page 31