ACPL-38JT-000E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-38JT-000E' PDF : 33 Pages View PDF
Other Recommended Components
The application circuit in Figure 61 includes an output pull-
down resistor, a DESAT pin protection resistor, a FAULT pin
capacitor (330 pF), and a FAULT pin pull-up resistor.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor
between the output and VEE is recommended to sink a
static current of several 650 A while the output is high.
Pull-down resistor values are dependent on the amount
of positive supply and can be adjusted according to the
formula, Rpull-down = [VCC2-3 * (VBE)] / 650 A.
DESAT Pin Protection
The freewheeling of flyback diodes connected across the
IGBTs can have large instantaneous forward voltage tran-
sients which greatly exceed the nominal forward voltage
of the diode. This may result in a large negative voltage
spike on the DESAT pin which will draw substantial current
out of the IC if protection is not used. To limit this current
to levels that will not damage the IC, a 100 ohm resistor
should be inserted in series with the DESAT diode. The
added resistance will not alter the DESAT threshold or the
DESAT blanking time.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 330 pF
capacitor (Fig. 66) should be connected between the fault
pin and ground to achieve adequate CMOS noise margins
at the specified CMR value of 15 kV/s. The added capaci-
tance does not increase the fault output delay when a de-
saturation condition is detected.
Protection on RESET Pin for High CMR
Large voltage spike on RESET due to excessive switching
noise coupling could trigger false FAULT output signal. In
such cases connecting a 330pF filtering capacitor between
RESET and GROUND or a clamping diode between RESET
to VCC1 will eliminate the false FAULT signal.
Driving with Standard CMOS/TTL for High CMR
Capacitive coupling from the isolated high voltage
circuitry to the input referred circuitry is the primary CMR
limitation. This coupling must be accounted for to achieve
high CMR performance. The input pins VIN+ and VIN- must
have active drive signals to prevent unwanted switching
of the output under extreme common mode transient
conditions. Input drive circuits that use pull-up or pull-
down resistors, such as open collector configurations,
should be avoided. Standard CMOS or TTL drive circuits
are recommended.
User-Configuration of the ACPL-38JT Input Side
The VIN+, VIN-, FAULT and RESET input pins make a wide
variety of gate control and fault configurations possible,
depending on the motor drive requirements. The
ACPL-38JT has both inverting and nonninverting gate
control inputs, an open collector fault output suitable for
wired ‘OR’ applications and an active low reset input.
Driving Input of ACPL-38JT in Non-Inverting/
Inverting Mode
The Gate Drive Voltage Output of the ACPL-38JT can be
configured as inverting or non-inverting using the VIN–
and VIN+ inputs. As shown in Figure 67, when a non-in-
verting configuration is desired, VIN– is held low by con-
necting it to GND1 and VIN+ is toggled. As shown in Figure
68, when an inverting configuration is desired, VIN+ is held
high by connecting it to VCC1 and VIN– is toggled.
Local Shutdown, Local Reset
As shown in Figure 69, the fault output of each ACPL-38JT
gate driver is polled separately, and the individual reset
lines are asserted low independently to reset the motor
controller after a fault condition.
Global-Shutdown, Global Reset
As shown in Figure 70, when configured for inverting
operation, the ACPL-38JT can be configured to shutdown
automatically in the event of a fault condition by tying the
FAULT output to VIN+. For high reliability drives, the open
collector FAULT outputs of each ACPL-38JT can be wire
‘OR’ed together on a common fault bus, forming a single
fault bus for interfacing directly to the micro-controller.
When any of the six gate drivers detects a fault, the fault
output signal will disable all six ACPL-38JT gate drivers
simultaneously and thereby provide protection against
further catastrophic failures.
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