ACPL-38JT-000E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-38JT-000E' PDF : 33 Pages View PDF
1 GND1
VE 16
2 VIN+
VLED2+ 15
3 VIN
DESAT 14
μC
4 VCC1
VCC2 13
5 RESET
VEE 12
6 FAULT
VC 11
7 VLED+
VOUT 10
8 VLED
VEE 9
Figure 67. Typical input configuration, noninverting.
1 GND1
VE 16
2 VIN+
VLED2+ 15
3 VIN
DESAT 14
μC
4 VCC1
VCC2 13
5 RESET
VEE 12
6 FAULT
VC 11
7 VLED+
VOUT 10
8 VLED
VEE 9
Figure 68. Typical Input Configuration, Inverting.
1 GND1
VE 16
2 VIN+
VLED2+ 15
3 VIN
DESAT 14
μC
4 VCC1
VCC2 13
5 RESET
VEE 12
6 FAULT
VC 11
7 VLED+
VOUT 10
8 VLED
VEE 9
Figure 69. Local shutdown, local reset configuration.
Auto-Reset
As shown in Figure 71, when the inverting VIN- input is
connected to ground (non-inverting configuration), the
ACPL-38JT can be configured to reset automatically by
connecting RESET to VIN+. In this case, the gate control
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no effect. Following a fault condition, the
gate driver remains in the latched fault state until the gate
control signal changes to the ‘gate low’ state and resets
the fault latch. If the gate control signal is a continuous
PWM signal, the fault latch will always be reset by the
next time the input signal goes high. This configuration
protects the IGBT on a cycle-by-cycle basis and automati-
cally resets before the next ‘on’ cycle. The fault outputs can
be wire ‘OR’ed together to alert the microcontroller, but
this signal would not be used for control purposes in this
(Auto-Reset) configuration. When the ACPL-38JT is con-
figured for Auto-Reset, the guaranteed minimum FAULT
signal pulse width is 3 s.
Resetting Following a Fault Condition
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must first be
asserted low in order to release the internal fault latch and
reset the FAULT output (high). Prior to asserting the RESET
pin low, the input (VIN) switching signals must be config-
ured for an output (VOL) low state. This can be handled
directly by the microcontroller or by hardwiring to syn-
chronize the RESET signal with the appropriate input
signal. Figure 72a shows how to connect the RESET to the
VIN+ signal for safe automatic reset in the non-inverting
input configuration. Figure 72b shows how to configure
the VIN+/RESET signals so that a RESET signal from the
microcontroller causes the input to be in the “output-
off” state. Similarly, Figures 72c and 72d show automatic
RESET and microcontroller RESET safe configurations for
the inverting input configuration.
27
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