ACPL-38JT View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-38JT' PDF : 33 Pages View PDF
1 GND1
0.1μF
2 VIN+
μC
−
+
5V
3 VIN-
4 VCC1
3.3kΩ
5 RESET
6 FAULT
330pF
7 VLED+
8 VLED-
VE 16
0.1μF
VLED2+ 15
DESAT 14
0.1μF
VCC2 13
100pF
100Ω DDESAT
+VF −
VEE 12
VC 11
0.1μF
VCC2 =18V
RG
+
−
Q1
VOUT 10
VEE 9
47kΩ +
−
VEE = -5V Q2
Figure 61. Recommended application circuit.
+
VCE
−
3-Phase
+ Output
VCE
−
Description of Operation/Timing
Figure 62 illustrates input and output waveforms under
the conditions of normal operation, a desat fault condition,
and normal reset behavior.
Normal Operation
During normal operation, VOUT of the ACPL-38JT is con-
trolled by either VIN+ or VIN-, with the IGBT collector-to-
emitter voltage being monitored through DDESAT. The
FAULT output is high and the RESET input should be held
high. See Figure 62.
Fault Condition
When the voltage on the DESAT pin exceeds 7 V while
the IGBT is on, VOUT is slowly brought low in order to
“softly” turn-off the IGBT and prevent large di/dt induced
voltages. Also activated is an internal feedback channel
which brings the FAULT output low for the purpose of
notifying the micro-controller of the fault condition. See
Figure 62.
Reset
The FAULT output remains low until RESET is brought
low. See Figure 62. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(VIN+ is LOW or VIN- is HIGH). This may be accomplished
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 71 and 72).
NON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
NORMAL
OPERATION
VIN- 0 V
5V
VIN+
VIN- 5 V
VIN+ 5 V
VDESAT
FAULT
CONDITION
7V
RESET
VOUT
FAULT
RESET
Figure 62. Timing diagram.
23
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