ACPL-38JT View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-38JT' PDF : 33 Pages View PDF
Slow IGBT Gate Discharge During Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the ACPL-38JT output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current that
could cause damaging voltage spikes due to lead and
wire inductance. During the slow turn off, the large output
pull-down device remains off until the output voltage falls
below VEE + 2 Volts, at which time the large pull down
device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor. The nominal blanking time is calculated in terms
of external capacitance (CBLANK), FAULT threshold voltage
(VDESAT), and DESAT charge current (ICHG) as tBLANK =
CBLANK x VDESAT / ICHG. The nominal blanking time with the
recommended 100 pF capacitor is 100 pF * 7 V / 250 A =
2.8 sec. The capacitance value can be scaled slightly to
adjust the blanking time, though a value smaller than 100
pF is not recommended.
This nominal blanking time also represents the longest
time it will take for the ACPL-38JT to respond to a DESAT
fault condition. If the IGBT is turned on while the collector
and emitter are shorted to the supply rails (switching into
a short), the soft shut-down sequence will begin after ap-
proximately 3 sec. If the IGBT collector and emitter are
shorted to the supply rails after the IGBT is already on, the
response time will be much quicker due to the parasitic
parallel capacitance of the DESAT diode. The recommend-
ed 100 pF capacitor should provide adequate blanking as
well as fault response times for most applications.
Under Voltage Lockout
The ACPL-38JT Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-38JT output low
during power-up. IGBTs typically require gate voltages of
15 V to achieve their rated VCE(ON) voltage. At gate voltages
below 13 V typically, their on-voltage increases dramatical-
ly, especially at higher currents. At very low gate voltages
(below 10 V), the IGBT may operate in the linear region and
quickly overheat. The UVLO function causes the output to
be clamped whenever insufficient operating supply (VCC2)
is applied. Once VCC2 exceeds VUVLO+ (the positive-going
UVLO threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
VCC2 is increased from 0 V (at some level below VUVLO+),
first the DESAT protection circuitry becomes active.
As VCC2 is further increased (above VUVLO+), the UVLO
clamp is released. Before the time the UVLO clamp is
released, the DESAT protection is already active. Therefore,
the UVLO and DESAT FAULT DETECTION features work
together to provide seamless protection regardless of
supply voltage (VCC2).
Behavioral Circuit Schematic
The functional behavior of the ACPL-38JT is represented
by the logic diagram in Figure 63 which fully describes the
interaction and sequence of internal and external signals
in the ACPL-38JT.
Input IC
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output is
in the open-collector state, and the state of the Reset pin
does not affect the control of the IGBT gate. When a fault
is detected, the FAULT output and signal input are both
latched. The fault output changes to an active low state,
and the signal LED is forced off (output LOW). The latched
condition will persist until the Reset pin is pulled low.
Output IC
Three internal signals control the state of the driver
output: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold, the
LED signal will control the driver output state. The driver
stage logic includes an interlock to ensure that the pull-up
and pull-down devices in the output stage are never on at
the same time. If an undervoltage condition is detected,
the output will be actively pulled low by the 50x DMOS
device, regardless of the LED state. If an IGBT desaturation
fault is detected while the signal LED is on, the Fault signal
will latch in the high state. The triple darlington AND the
50x DMOS device are disabled, and a smaller 1x DMOS
pull-down device is activated to slowly discharge the
IGBT gate. When the output drops below two volts, the
50x DMOS device again turns on, clamping the IGBT gate
firmly to Vee. The Fault signal remains latched in the high
state until the signal LED turns off.
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