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ACS411CS View Datasheet(PDF) - Semtech Corporation

Part Name
Description
MFG CO.
ACS411CS
Semtech
Semtech Corporation Semtech
'ACS411CS' PDF : 43 Pages View PDF
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Transmit monitor TXMON and TXFLAG
Transmission Clock TCLK
TXMON is used to monitor the current delivered to
the LED or Laser. TXMON is a current source that
proportionally mirrors the current flow through the
LED or Laser. By placing an appropriate external
resistor R
between TXMON and GND, the
TXMON
voltage developed (referenced to GND), will be
proportional to the transmit current. During the Laser
setup procedure TXMON should be monitored to
ensure that the Laser manufacturer's maximum
current specification is not exceeded.
The transmit current monitor is a current source
flowing from VDD out of pin TXMON. This current is
representative of the Laser/LED drive current.
There are 16 independent Transmit clocks
TCLK(16:1) on the ACS4110. For the purpose of
this specification, these signals will be referred to
collectively as TCLK. The ACS4110 gives a choice
between internally and externally generated transmit
clocks. When the CKC pin is held Low, the set of
TCLK clocks are configured as outputs producing a
clock at the frequency defined by DR(3:1).
When the CKC pin is held High, the set of TCLK
clocks are configured as inputs, and will accept an
externally produced transmission clock with a
tolerance of up to 250ppm with respect to the
transmission rate determined by DR(3:1).
I = I /50 + I /100
TXMON
BIAS
MOD
IBIAS is the Low level bias current.
I is the peak Modulation level bias current. The
MOD
average modulation current is half this value.
The data appearing on TPOS/TNEG is valid on the
rising or falling edge of the TCLK clock dependent
on the setting of TRSEL (see Figure 22. Timing
diagrams). This is the case for both internally and
externally generated transmission clocks.
Average drive current, I = (I + I ) /2
AVG
BIAS
MOD
Therefore I = I /50
TXMON
AVG
TXMON may also be employed during normal
operation to continuously check the Laser current.
The voltage developed across R
is compared
TXMON
within an internally generated reference voltage of
1.25V. In the event that the reference voltage is
exceeded, the TXFLAG is set High, otherwise it is
set Low. In this way, the value of resistor on TXMON
can be chosen to activate TXFLAG at any desired
transmit current
e.g.
If
R
TXMON
=
1K,
then TXFLAG will be set if I
AVG
exceeds 62.5mA.
If desired, TXFLAG activation can be delayed by
adding a damping capacitor between TXMON and
GND.
Receive Monitor RXMON and RXFLAG
The ACS9020 incorporates a power meter which
generates a current source which is proportional to the
received optical current.
There is an internal resistor of value of 50K+/- 20 %
connected between RXMON and GND which
converts the current into a voltage.
RXMON is compared with 1.25V. If RXMON exceeds
1.25V, then output RXFLAG is set = 1, otherwise
RXFLAG is set = 0. With the internal resistor of
50K. By adding an external parallel resistor
between RXMON and GND, this threshold may be
increased.
Receive Clock RCLK
There are 16 independent Receive clocks
RCLK(16:1) on the ACS4110. For the purpose of
this specification, these signals will be referred to
collectively as RCLK.
The data appearing on RPOS/RNEG is valid on the
rising or falling edge of the RCLK clock dependent
on the setting of RESEL (see Figure 22. Timing
diagrams). To ensure that the average receive
frequency is the same as the transmitted frequency,
RCLK is generated from a Phase-Lock Loop (PLL)
system (except where master mode has been
selected). The PLL makes periodic corrections to
the output RCLK clock by subtracting or adding a
single crystal clock bit-period, so that the average
frequency of the RCLK clock tracks the average
frequency of the transmit clock of the far-end modem
(or system master clock). This decompression/de-
jittering function is covered in more detail in section
headed, Jitter Characteristics.
The recovery and de-jittering functions comply to jitter
tolerance and jitter transfer specifications of the
selected data rates. The algorithm that determines
the transfer function and response of the PLLs is
modified (shaped) according to the selected data rate.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
6
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