ACS411CS View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS411CS' PDF : 43 Pages View PDF
TmCLK and the reference clock for the (digital) clock
recovery and de-jittering PLLs (DPLL) for RmCLK
are derived digitally from the system clock for
256kbps by the division factors shown in Table 8. If
lower data rates than 256kbps are selected, the
256kHz clock will be divided down by a factor 2/4/8/
16/32 determined by MSEL(3:1).
Mode
FSys/256 kbps
16 x T1
16 x E1
7 x T2
4 x E2
1 x E3
1 x T3
1 x OC1
271.40625
264
271.21875
264
268.5
262.125
303.75
Table 8: System Clock Division Factors for
Maintenance Clock Generation (256kbps)
ERRC and ERRL - Error Detection
These signals can be used to give an indication of
the quality of the optical link. Even when a DC signal
is applied to the data, maintenance and TCLK inputs,
the ACS411CS modem transmits data over the link
in each direction at the Fsys system frequency. This
transmit and control data is used to maintain the
timing and synchronisation.
The transmit and control data is constantly monitored
to make sure it is compatible with the 8B10B format.
If a coding error is detected ERRL will go High and
will remain High until reset. ERRL may be reset by
asserting PORB, or by removing the fiber optic cable
from one side of the link thereby forcing the device
temporarily out of lock.
ERRC produces a pulse on detection of each coding
error. These pulses may be accumulated by means
of an external electronic counter. In the
microprocessor modes, the value on an internal
accumulating 8 bit counter can be read via the bus
interface address 0x1D.
Please note that ERRL and ERRC detect 8B10B
coding errors and not data errors, nevertheless
because of the complexity of the coding rules
employed on the ACS411CS, the absence of detected
errors on these pins will give a good indication of a
high quality link.
11
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
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