ACS411CS View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS411CS' PDF : 43 Pages View PDF
Microprocessor Interface
MULTIPLEXED mode
Bus Interface Mode Selection
The ACS4110 incorporates an 8-bit parallel
microprocessor bus interface, which can be configured
for the following modes via the bus interface mode
control pins UPSEL(3:1) as defined in Table 9.
UPSEL(3:1) Mode
Description
111 (7)
110 (6)
101 (5)
100 (4)
011 (3)
010 (2)
001 (1)
000 (0)
OFF
Interface disabled
OFF
Interface disabled
SERIAL
Serial uP bus interface
MOTOROLA Motorola interface
INTEL
Intel compatible bus interface
MULTIPLEXED Multiplexed bus interface
EPROM
EPROM read mode
OFF
Interface disabled
Table 9: Microprocessor Interface Mode Selection
Note: Bit 0 is the least significant bit for all modes used
here, and the byte structure complies to little endian
format (byte 0 is least significant and stored at lowest
address).
In OFF Mode, the bus interface is disabled. Control of
the device is solely via I/O pins. This will result in limited
programmability, as for example individual set-ups for
remote loop-back and local loop-back for each channel
are not possible, only a collective one. In this mode, all
BUS I/O pins are tri-stated or used as additional input
pins (ie. POL(3:1), CKLOCAL).
The MULTIPLEXED mode (UPSEL = 2) enables the
ACS4110 to interface with a microprocessor using a
combined multiplexed address/data bus. The bus
interface pins are defined in Table 11.
Pin
Dir
Description
CSB
ALE
RDB
WRB
AD(7:0)
RDY
I
Active low chip select
I
Address latch enable
I
Active low read enable
I
Active low write enable
IO Address / Data bus
O
Ready
Table 11: uP Bus Interface Pins for MULTIPLEXED mode.
INTEL mode
The INTEL mode (UPSEL = 3) enables the ACS4110
to interface with a Intel 80x86 type microprocessor
bus. The bus interface pins used are defined in Table
12.
Pin
CSB
RDB
WRB
A(4:0)
AD(7:0)
RDY
Dir
Description
I
Active low chip select
I
Active low read enable
I
Active low write enable
I
Address bus
IO Data bus
O
Ready
Table 12: uP Bus Interface Pins for INTEL mode.
EPROM mode
The EPROM mode (UPSEL = 1) enables the device to
read its set-up from a memory device. An internal state
machine controls the access to the memory. All
addresses in the memory map are read, and the device
is set up according to the corresponding data. The
access time is scaled to interface with the AMD
AM27C020 at lowest speed (250ns) specification.
MOTOROLA mode
The MOTOROLA mode (UPSEL = 4) enables the
ACS4110 to interface with a Motorola 680x0 type
microprocessor bus. The bus interface pins used are
defined in Table 13.
Pin
Dir
Description
The valid read addresse 0, 0xAA is used to check if a
memory device is actually attached to the device. If no
memory is attached, the bus interface reverts to the
default OFF mode. All other read addresses are not
valid. The bus interface pins used in EPROM mode are
defined in Table 10.
CSB
I
WRB
I
A(4:0) I
AD(7:0) IO
RDY
O
Active low chip select
Read / write bar select
Address bus
Data bus
Active low data transfer
acknowledge (DTACK)
Table 13: uP Bus Interface Pins for MOTOROLA mode.
Pin
Dir
Description
CSB
O
A(4:0) O
AD(7:0) I
Active low chip select/output enable
Address output to EPROM
Data input from EPROM
Table 10: uP Bus Interface Pins for EPROM mode.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
12
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