ACS411CS View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS411CS' PDF : 43 Pages View PDF
uP Interface timing - MOTOROLA mode
In MOTOROLA mode, the device is configured to
interface with a microprocessor using a 680x0 type
bus. The following figures show the timing diagrams
of write and read accesses for this mode.
The Dtack high time Trdy is at least 2 CLKX cycles
after CSB going low.
CSB
WRB
A
AD
RDY
(DTACK)
X
Z
Z
tpw1
tsu2
th2
tsu1
address
th1
td1
td3
data
td2
tpw2
th3
td4
X
X
Z
Z
Symbol
Parameter
Min
tsu1 Setup A valid to CSB ↓
0
tsu2 Setup WRB valid to CSB ↓
5*
td1 Delay CSB ↓ to AD valid
td2 Delay CSB ↓ to DTACK ↑
td3 Delay CSB ↑ to AD High-Z
td4 Delay CSB ↑ to RDY High-Z
tpw1 CSB low time
60
tpw2 DTACK high time
20
th1 Hold A valid after CSB↑
0
th2 Hold WRB high after CSB ↑
5*
th3 Hold CSB low after DTACK ↓
0
tp
Time between consecutive accesses
(CSB ↑ to CSB ↓)
60
Typ Max
10 *
10 *
10 *
10 *
60
Figure 8: Read access timing in MOTOROLA Mode.
Note: preliminary timing information. Timing values marked with * TBA.
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
18
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