ACS760ELFTR-20B-T View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'ACS760ELFTR-20B-T' PDF : 15 Pages View PDF
ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
OPERATING CHARACTERISTICS, continued valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min. Typ. Max. Units
Maximum Short Circuit/Overcurrent
Fault Threshold5
ISC
60
110 160
A
Short Circuit/Overcurrent Fault Gate
Delay
tSC Measured from FAULT signal to VGATE < 1 V, Includes tGF
–
2
3
μs
VOLTAGE FAULT PERFORMANCE CHARACTERISTICS
Internal Pull Down Resistance Between
EN and GND
REN
TA = 25°C
–
100
–
kΩ
EN Voltage Threshold6
S1 Short Circuit Detection Current7
S1 Short Circuit Detection Delay
VENH IC enabled when VEN > VENH
1.93
–
–
V
VENL IC disabled when VEN < VENL
–
–
1
V
IS1S VGATE = 0 V or VGATE = 12 V
0.9
1.5
2.1
A
tS1S
Measured from disablement of the device to detection of an
S1 fault
–
–
15
μs
S1SHORT Output Voltage
VS1SOL IS1SHORT = 3 mA sink current
S1SHORT Output Leakage Current
IS1SIH VS1SHORT = 3.3 V
FAULT Output Voltage
VFAULTOL IFAULT = 3 mA sink current
FAULT Output Leakage Current
IFAULTIH VFAULT = 3.3 V
GATE DRIVE PERFORMANCE CHARACTERISTICS
–
–
0.4
V
–
–
5
μA
–
–
0.4
V
–
–
5
μA
Internal Charge Pump Voltage
Average GATE Drive Current
Charge Pump Switching Frequency
GATE Rise Time
VCP TA = 25°C
– VCC + 10 –
IGD VCC = 12 V, TA = 25°C
25
50
–
fCP TA = 25°C
–
1
–
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,
measured from VGATE = 0 V to 15 V, CG pin open, no output –
1
–
load capacitance
tGR
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,
measured from VGATE = 0 V to 15 V, 3.75 μF capacitor con-
–
500
–
nected between CG and GND pins
V
μA
MHz
ms
ms
GATE Sink Resistance
GATE Discharge Current
GATE Shutdown Delay
GATE Maximum Fall Time
RGsink
IGD
tGSD
tGF
VGATE = VCC + 10 V
Measured from fault event to start of GATE pull down
Measured from VGATE = 90% of maximum to VGATE < 1 V,
external MOSFET S1 gate capacitance = 5.8 nF. EN pin
switched from high to low, FAULT or S1SHORT signal
–
20
30
Ω
–
1000
–
mA
–
200
–
ns
–
800
–
ns
CG Output Current
ISLEW TA = 25°C
18
20
22
μA
1The small signal, ac bandwidth of this device is approximately 90 kHz.
2This test requires currents sufficient to swing the output driver between the fully off state and the saturated state. Assumes that the VIOUT pin is con-
nected to an analog-to-digital converter that saturates at 2.5 V. The VIOUT signal is linear above 2.5 V, however, this test is NOT intended to indicate a
range of linear operation.
3Assumes that a 1% resistor with a flat temperature coefficient is connected between the ISET and GND pins.
4Can exceed tIPFH(max) delay period via the use of a larger external capacitor. Voltage trip point on the high side of the capacitor is 3.85 V.
5This parameter is internally programmed and cannot be controlled by the end user.
6The FAULT output signal is latched. After a latched fault event, the device will be reset only when either: (a) VEN drops below VENL, or (b) the power to
the device (applied to the IP+ pins) is toggled off and then back on.
7The voltage on the gate of the external MOSFET S1 does not need to be < 1 V in order for the device to detect an S1 short circuit condition. The
device does detect a faulty S1 when the gate of S1 is shorted to the S1 source or drain terminal.
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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