ACS8509 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8509' PDF : 68 Pages View PDF
ACS8509 SETS
ADVANCED COMMUNICATIONS
Phase Build-Out
FINAL
Microprocessor Interface
DATASHEET
Phase Build-Out (PBO) is the function to minimize phase
transients on the output SEC clock during input reference
switching. If the currently selected input reference clock
source is lost (due to a short interruption, out of frequency
detection, or complete loss of reference), the second, next
highest priority reference source will be selected. During
this transition, the Lost_Phase mode is entered.
The typical phase disturbance on clock reference source
switching will be less than 12 ns on the ACS8509. For
clock reference switching caused by the main input failing
or being disconnected, then the phase disturbance on the
output will still be less than the 120 ns allowed for in the
G.813 spec. The actual value is dependent on the
frequency being locked to.
ITU-T G.813 states that the max allowable short term
phase transient response, resulting from a switch from
one clock source to another, with Holdover mode entered
in between, should be a maximum of 1 µs over a 15
second interval. The maximum phase transient or jump
should be less than 120 ns at a rate of change of less
than 7.5 ppm and the Holdover performance should be
better than 0.05 ppm.
On the ACS8509, PBO can be enabled, disabled or frozen
using the µP interface. By default, it is enabled. When PBO
is enabled, it can also be frozen, which will disable the
PBO operation on the next input reference switch, but will
remain with the current offset. If PBO is disabled while the
device is in the Locked mode, there will be a phase jump
on the output SEC clocks as the DPLL locks back to 0
degree phase error.
The ACS8509 incorporates a microprocessor interface,
which can be configured for the following modes via the
bus interface mode control pins UPSEL(2:0) as defined in
Table 12.
Table 12 Microprocessor Interface Mode Selection
UPSEL(2:0)
Mode
Description
111 (7) OFF
Interface disabled
110 (6) OFF
Interface disabled
101 (5) SERIAL
Serial uP bus interface
100 (4) MOTOROLA Motorola interface
011 (3) INTEL
Intel compatible bus interface
010 (2) MULTIPLEXED Multiplexed bus interface
001 (1) EPROM
EPROM read mode
000 (0) OFF
Interface disabled
Motorola Mode
Parallel data + address: this mode is suitable for use with
Motorola's 68x0 type bus.
Intel Mode
Parallel data + address: this mode is suitable for use with
Intel's 80x86 type bus.
Multiplexed Mode
Data/address: this mode is suitable for use with
microprocessors which share bus signals between
address and data (e.g., Intel's 80x86 family).
Serial Mode
This mode is suitable for use with microprocessor which
use a serial interface.
EPROM Mode
This mode is suitable for simple standalone applications
where it is required to change the default loading of the
register values to suit different applications.
This can be done by loading values from an external ROM.
The data is read from the ROM automatically after power-
up when the UPSEL(2:0) pins are set to “001”. Each
register value is stored sequentially, with ROM address 0
corresponding to register address 0 and so on.
Revision 2.00/January 2006 © Semtech Corp.
Page 17
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