ACS8510 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8510' PDF : 69 Pages View PDF
ACS8510 Rev2.1 SETS
ADVANCED COMMUNICATIONS
FINAL
Table 3. Other Pins
PIN
SYMBOL
IO TYPE
NAME/DESCRIPTION
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary
2
TRST
I
TTLD Scan mode. TRST = 0 for normal device operation (JTAG logic
transparent). If not used connect to GND or leave floating.
7
TMS
I
TTLU
JTAG Test Mode Select: Boundary Scan enable. Sampled on
rising edge of TCK. If not used connect to VDD or leave floating.
8
INTREQ
O
TTL
CMOS
Interrupt Request: Active high software Interrupt output
JTAG Clock: Boundary Scan clock input. If not used connect to
GND or leave floating. This pin may require a capacitor placed
9
TCK
I
TTLD between the pin and the nearest GND, to reduce noise pickup. A
value of 10 pF should be adequate, but the value is dependent on
PCB layout.
10
REFCLK
I
TTL
Reference Clock: 12.8 MHz (refer to section headed Local
Oscillator Clock)
18
SRCSW
I
TTLD Source Switching: Force Fast Source Switching
21
TDO
O
TTL JTAG Output: Serial test data output. Updated on falling edge of
CMOS TCK. If not used leave floating.
23
TDI
I
TTLU
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
If not used connect to VDD or leave floating.
24
I1
I
AMI Input reference 1: composite clock 64 kHz + 8 kHz
25
I2
I
AMI Input reference 2: composite clock 64 kHz + 8 kHz
27
TO8NEG
O
AMI
Output reference 8: composite clock, 64 kHz + 8 kHz negative
pulse
28
TO8POS
O
AMI
Output reference 8: composite clock, 64 kHz + 8 kHz positive
pulse
30
FrSync
O
TTL Output reference 10: 8 kHz Frame Sync clock output (square
CMOS wave)
31
MFrSync
O
TTL Output reference 11: 2 kHz Multi-Frame Sync clock output
CMOS (square wave)
34
35
TO6POS
TO6NEG
O
LVDS
PECL
Output reference 6: default 38.88 MHz. Also Dig1 (1.544
MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04
MHz. Default type LVDS.
36
37
TO7POS
TO7NEG
O
PECL Output reference 7: default 19.44 MHz. Also 51.84 MHz, 77.76
LVDS MHz, 155.52 MHz. Default type PECL.
40
41
I5POS
I5NEG
I
LVDS
PECL
Input reference 5: default 19.44 MHz, default type LVDS
42
43
I6POS
I6NEG
I
PECL
LVDS
Input reference 6: default 19.44 MHz, default type PECL
Revision 2.00/September 2003 Semtech Corp.
7
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